參數(shù)資料
型號(hào): M95080-WDL5T
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 64/32/16/8千位串行SPI總線的EEPROM高速時(shí)鐘
文件頁數(shù): 12/39頁
文件大?。?/td> 590K
代理商: M95080-WDL5T
M95640, M95320
12/39
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 4.
If an invalid instruction is sent (one not contained
in Table 4), the device automatically deselects it-
self.
Table 4. Instruction Set
Figure 9. Write Enable (WREN) Sequence
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in Figure 9, to send this instruction to the
device, Chip Select (S) is driven Low, and the bits
of the instruction byte are shifted in, on Serial Data
Input (D). The device then enters a wait state. It
waits for a the device to be deselected, by Chip
Select (S) being driven High.
Instruc
tion
Description
Instruction
Format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
C
D
AI02281E
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
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