參數(shù)資料
型號: M95080-WDS3T
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 16Kbit和8Kbit SPI總線串行EEPROM的高速時鐘
文件頁數(shù): 13/39頁
文件大小: 590K
代理商: M95080-WDS3T
13/39
M95640, M95320
Figure 10. Write Disable (WRDI) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 10, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
– Power-up
– WRDI instruction execution
– WRSR instruction completion
– WRITE instruction completion.
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
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