- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377840 > M95128-DW3PV (意法半導(dǎo)體) 128 Kbit Serial SPI bus EEPROM with high speed clock PDF資料下載
參數(shù)資料
| 型號： | M95128-DW3PV |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| 中文描述： | 128千位的SPI高速時鐘總線的EEPROM |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 207K |
| 代理商： | M95128-DW3PV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
M95128, M95128-W, M95128-R
Signal description
9/41
3
Signal description
See
Figure 1: Logic diagram
and
Table 1: Signal names
, for a brief overview of the signals
connected to this device.
3.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
3.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M95128-DW3TGP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3TGV | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-MN6PP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-MN6PV | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-MN6TGP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95128-DW3T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95128-DW3TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95128-DW3TG/A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit serial SPI bus EEPROM with high speed clock |
| M95128-DW3TG/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit serial SPI bus EEPROM with high speed clock |
| M95128-DW3TG/PC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit serial SPI bus EEPROM with high speed clock |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。