參數(shù)資料
型號: M95128-R
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 128 Kbit Serial SPI bus EEPROM with high speed clock
中文描述: 128千位的SPI高速時鐘總線的EEPROM
文件頁數(shù): 24/41頁
文件大小: 207K
代理商: M95128-R
Connecting to the SPI bus
M95128, M95128-W, M95128-R
24/41
7.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
Figure 13
, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 13.
SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
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