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參數(shù)資料
| 型號： | M95128-RDW3GP |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| 中文描述： | 128千位的SPI高速時鐘總線的EEPROM |
| 文件頁數(shù)： | 33/41頁 |
| 文件大?。?/td> | 207K |
| 代理商： | M95128-RDW3GP |
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M95128, M95128-W, M95128-R
DC and AC parameters
33/41
Table 19.
AC characteristics (M95128-R)
Test conditions specified in
Table 10
and
Table 9
Symbol
Alt.
Parameter
Min.
(1)
1.
This is preliminary data.
Max.
(1)
Unit
f
C
f
SCK
Clock Frequency
D.C.
2
MHz
t
SLCH
t
CSS1
S Active Setup Time
200
ns
t
SHCH
t
CSS2
S Not Active Setup Time
200
ns
t
SHSL
t
CS
S Deselect Time
200
ns
t
CHSH
t
CSH
S Active Hold Time
200
ns
t
CHSL
t
CH (2)
t
CL (2)
t
CLCH (3)
t
CHCL (3)
S Not Active Hold Time
200
ns
2.
t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max)
Value guaranteed by characterization, not 100% tested in production.
t
CLH
Clock High Time
200
ns
t
CLL
Clock Low Time
200
ns
3.
t
RC
Clock Rise Time
1
μs
t
FC
Clock Fall Time
1
μs
t
DVCH
t
DSU
Data In Setup Time
40
ns
t
CHDX
t
DH
Data In Hold Time
50
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
140
ns
t
HLCH
Clock Low Hold Time after HOLD Active
90
ns
t
CLHL
Clock Low Set-up Time before HOLD Active
0
ns
t
CLHH
Clock Low Set-up Time before HOLD not
Active
0
ns
t
SHQZ (3)
t
DIS
Output Disable Time
250
ns
t
CLQV
t
V
Clock Low to Output Valid
150
ns
t
CLQX
t
QLQH (3)
t
QHQL (3)
t
HO
Output Hold Time
0
ns
t
RO
Output Rise Time
100
ns
t
FO
Output Fall Time
100
ns
t
HHQV
t
HLQZ (3)
t
LZ
HOLD High to Output Valid
100
ns
t
HZ
HOLD Low to Output High-Z
250
ns
t
W
t
WC
Write Time
10
ms
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| M95128-RDW3GV | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit Serial SPI bus EEPROM with high speed clock |
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