參數(shù)資料
型號(hào)： M95128-RDW3TGP
廠商： 意法半導(dǎo)體
元件分類(lèi)： DRAM
英文描述： 128 Kbit Serial SPI bus EEPROM with high speed clock
中文描述： 128千位的SPI高速時(shí)鐘總線的EEPROM
文件頁(yè)數(shù)： 15/41頁(yè)
文件大?。?/td> 207K
代理商： M95128-RDW3TGP
M95128, M95128-W, M95128-R
Instructions
15/41
5.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in
Figure 7
.
The status and control bits of the Status Register are as follows:
5.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
5.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
5.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in
Table 4
) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
5.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
相關(guān)PDF資料
PDF描述
M95128-RDW3TGV 128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-RDW3TPP 128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-RDW3TPV 128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-RDW3TV 128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-RDW3V 128 Kbit Serial SPI bus EEPROM with high speed clock
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M95128-RDW3TGV 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-RDW3TP 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Kbit Serial SPI bus EEPROM with high speed clock
M95128-RDW3TP/A 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Kbit serial SPI bus EEPROM with high speed clock
M95128-RDW3TP/P 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Kbit serial SPI bus EEPROM with high speed clock
M95128-RDW3TP/PC 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Kbit serial SPI bus EEPROM with high speed clock
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