參數(shù)資料
型號: M95128-RDW3TV
廠商: 意法半導體
元件分類: DRAM
英文描述: 128 Kbit Serial SPI bus EEPROM with high speed clock
中文描述: 128千位的SPI高速時鐘總線的EEPROM
文件頁數(shù): 14/41頁
文件大?。?/td> 207K
代理商: M95128-RDW3TV
Instructions
M95128, M95128-W, M95128-R
14/41
5.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
Figure 6
, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 6.
Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
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