參數(shù)資料
型號: M95160-WBN6T
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 64/32/16/8千位串行SPI總線的EEPROM高速時鐘
文件頁數(shù): 16/40頁
文件大?。?/td> 648K
代理商: M95160-WBN6T
M95160, M95080
16/40
(BP1, BP0) bits of the Status Register, are
also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
Table 7. Address Range Bits
Note: b15 to b11 are Don’t Care on the M95160.
b15 to b10 are Don’t Care on the M95080.
Figure 10. Write Status Register (WRSR) Sequence
Device
M95160
M95080
Address Bits
A10-A0
A9-A0
C
D
AI02282D
S
Q
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
High Impedance
Instruction
Status
Register In
0
7
6
5
4
3
2
0
1
MSB
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