參數(shù)資料
型號: M95160DL
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 64/32/16/8千位串行SPI總線的EEPROM高速時鐘
文件頁數(shù): 17/40頁
文件大小: 648K
代理商: M95160DL
17/40
M95160, M95080
Read from Memory Array (READ)
As shown in
Figure 11.
, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) Sequence
Note: Depending on the memory size, as shown in
Table 7.
, the most significant address bits are Don’t Care.
C
D
AI01793D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
7
6
5
4
3
1
7
0
High Impedance
Data Out 1
Instruction
16-Bit Address
0
MSB
MSB
2
31
Data Out 2
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