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參數(shù)資料
| 型號： | M95160MN |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 64/32/16/8千位串行SPI總線的EEPROM高速時鐘 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 648K |
| 代理商： | M95160MN |
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M95160, M95080
10/40
Status Register
Figure 6.
shows the position of the Status Register
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit.
The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit.
The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits.
The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit.
The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 3. Status Register Format
Data Protection and Protocol Control
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction
completion
–
Write Status Register (WRSR) instruction
completion
–
Write (WRITE) instruction completion
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sen-
tence:
–
The ‘last bit of the instruction’ can be the
eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction
(except for Read Status Register (RDSR) and
Read (READ) instructions).
–
The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
■
■
■
■
Table 4. Write-Protected Block Size
b7
b0
SRWD
0
0
0
BP1
BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95160
M95080
0
0
none
none
none
0
1
Upper quarter
0600h - 07FFh
0300h - 03FFh
1
0
Upper half
0400h - 07FFh
0200h - 03FFh
1
1
Whole memory
0000h - 07FFh
0000h - 03FFh
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相關(guān)代理商/技術(shù)參數(shù) |
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| M95160-MN1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-MN3 | 功能描述:電可擦除可編程只讀存儲器 5.5V 16K (2Kx8) RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M95160-MN3G/G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95160-MN3G/S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95160-MN3P/G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
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