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參數(shù)資料
| 型號(hào)： | M95256-DL3T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 一百二十八分之二百五十六千位串行SPI總線的EEPROM高速時(shí)鐘 |
| 文件頁(yè)數(shù)： | 8/39頁(yè) |
| 文件大?。?/td> | 580K |
| 代理商： | M95256-DL3T |
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M95256, M95128
8/39
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
–
CPOL=0, CPHA=0
–
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in
Figure 5.
, is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
–
C remains at 0 for (CPOL=0, CPHA=0)
–
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI Modes Supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
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