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  • 參數(shù)資料
    型號(hào): M95256-DW6G
    廠(chǎng)商: 意法半導(dǎo)體
    元件分類(lèi): EEPROM
    英文描述: 256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock
    中文描述: 256Kbit和128Kbit的EEPROM串行SPI總線(xiàn)高速時(shí)鐘
    文件頁(yè)數(shù): 13/39頁(yè)
    文件大?。?/td> 580K
    代理商: M95256-DW6G
    13/39
    M95256, M95128
    Write Enable (WREN)
    The Write Enable Latch (WEL) bit must be set pri-
    or to each WRITE and WRSR instruction. The only
    way to do this is to send a Write Enable instruction
    to the device.
    As shown in
    Figure 8.
    , to send this instruction to
    the device, Chip Select (S) is driven Low, and the
    bits of the instruction byte are shifted in, on Serial
    Data Input (D). The device then enters a wait
    state. It waits for a the device to be deselected, by
    Chip Select (S) being driven High.
    Figure 8. Write Enable (WREN) Sequence
    Write Disable (WRDI)
    One way of resetting the Write Enable Latch
    (WEL) bit is to send a Write Disable instruction to
    the device.
    As shown in
    Figure 9.
    , to send this instruction to
    the device, Chip Select (S) is driven Low, and the
    bits of the instruction byte are shifted in, on Serial
    Data Input (D).
    The device then enters a wait state. It waits for a
    the device to be deselected, by Chip Select (S) be-
    ing driven High.
    The Write Enable Latch (WEL) bit, in fact, be-
    comes reset by any of the following events:
    Power-up
    WRDI instruction execution
    WRSR instruction completion
    WRITE instruction completion.
    Figure 9. Write Disable (WRDI) Sequence
    C
    D
    AI02281E
    S
    Q
    2
    1
    3
    4
    5
    6
    7
    High Impedance
    0
    Instruction
    C
    D
    AI03750D
    S
    Q
    2
    1
    3
    4
    5
    6
    7
    High Impedance
    0
    Instruction
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