參數(shù)資料
型號: M95256-WDW6TG
廠商: 意法半導體
元件分類: EEPROM
英文描述: 256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock
中文描述: 256Kbit和128Kbit的EEPROM串行SPI總線高速時鐘
文件頁數(shù): 13/39頁
文件大小: 580K
代理商: M95256-WDW6TG
13/39
M95256, M95128
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in
Figure 8.
, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
Figure 8. Write Enable (WREN) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in
Figure 9.
, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 9. Write Disable (WRDI) Sequence
C
D
AI02281E
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
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相關代理商/技術參數(shù)
參數(shù)描述
M95256-WDW6TG/A 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock
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M95256WDW6TP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock
M95256-WDW6TP 功能描述:電可擦除可編程只讀存儲器 256 Kbit Serial Bus 電可擦除可編程只讀存儲器 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8