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參數(shù)資料
| 型號： | M95256-WMN3 |
| 廠商： | 意法半導體 |
| 元件分類： | EEPROM |
| 英文描述： | 256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 256Kbit和128Kbit的EEPROM串行SPI總線高速時鐘 |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 580K |
| 代理商： | M95256-WMN3 |
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M95256, M95128
6/39
SIGNAL DESCRIPTION
During all operations, V
CC
must be held stable and
within the specified valid range: V
CC
(min) to
V
CC
(max).
All of the input and output signals must be held
High or Low (according to voltages of V
IH
, V
OH
, V
IL
or V
OL
, as specified in
Table 13.
to
Table 17.
).
These signals are described next.
Serial Data Output (Q).
This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D).
This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C).
This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S).
When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD).
The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W).
The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write instructions.
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|---|---|
| M95256-WMN3/A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
| M95256-WMN3/V | 制造商:STMicroelectronics 功能描述:EEPROM SERL-SPI 256KBIT 32KX8 3.3V/5V 8PIN SO - Rail/Tube |
| M95256WMN3G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-WMN3G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95256-WMN3G/A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
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