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參數(shù)資料
| 型號(hào)： | MAC7100CVF |
| 廠商： | Motorola, Inc. |
| 英文描述： | MAC7100 Microcontroller Family Hardware Specifications |
| 中文描述： | MAC7100微控制器系列硬件規(guī)格 |
| 文件頁(yè)數(shù)： | 19/48頁(yè) |
| 文件大?。?/td> | 1514K |
| 代理商： | MAC7100CVF |
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19
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Electrical Characteristics
3.9
External Bus Timing Specifications
Table 22 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
Figure 6. General Input Timing Requirements
Table 22. External Bus Input Timing Specifications
Num
C
Rating
1
1
2
Timing specifications have been indicated taking into account the full drive strength for the pads.
TA pins are being referred to as control inputs.
Symbol
Min
Max
Unit
L1
CLKOUT
t
CYC
23
—
ns
Control Inputs
L2a
Control input valid to CLKOUT high
2
CLKOUT high to control inputs invalid
2
t
CVCH
t
CHCII
13
—
ns
L3a
0
—
ns
Data Inputs
L4
Data input (DATA[15:0]) valid to CLKOUT high
t
DIVCH
t
CHDII
9
—
ns
L5
CLKOUT high to data input (DATA[15:0]) invalid
0
—
ns
CLKOUT(45MHz)
1.5 V
1.5 V
Valid
Invalid
Invalid
t
SETUP
t
HOLD
Input Setup & Hold
Input Rise Time
V
H
= V
IH
V
L
= V
IL
t
RISE
= 1.5 ns
Input Fall Time
V
H
= V
IH
V
L
= V
IL
t
FALL
= 1.5 ns
CLKOUT
Inputs
1.5 V
L4
L5
F
Freescale Semiconductor, Inc.
n
.
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