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參數(shù)資料
| 型號： | MACH120-15JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MACH120-15JC |
MACH120-12/15
19
MACH
1
&
2
Families
FMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Be-
cause the exibility inherent in programmable logic devices offers a choice of clocked ip-op
designs, fMAX is specied for three types of synchronous designs.
The rst type of design is a state machine with feedback signals sent off-chip. This external feedback
could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest
path dening the period is the sum of the clock-to-output time and the input setup time for the exter-
nal signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in
conjunction with an equivalent speed device. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state machine with internal feedback only. In this
case, ip-op inputs are dened by the device inputs and ip-op outputs. Under these condi-
tions, the period is limited by the internal delay from the ip-op outputs through the internal
feedback and logic to the ip-op inputs. This fMAX is designated “fMAX internal”. A simple in-
ternal counter is a good example of this type of design; therefore, this parameter is sometimes
called “fCNT.”
The third type of design is a simple data path application. In this case, input data is presented
to the ip-op and clocked through; no feedback is employed. Under these conditions, the pe-
riod is limited by the sum of the data setup time and the data hold time (tS + tH). However, a
lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually,
this minimum clock period determines the period for the third fMAX, designated “fMAX no feed-
back.”
For devices with input registers, one additional fMAX parameter is specied: fMAXIR. Because this
involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period
will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock
widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is
specied as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same
path, the overall frequency will be limited by tICS.
All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX
internal is measured directly.
LOGIC
REGISTER
CLK
LOGIC
REGISTER
CLK
tCO
tS
fMAX Internal (fCNT)
fMAX External 1/(ts + tCO)
LOGIC
REGISTER
CLK
fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL)
(SECOND
CHIP)
REGISTER
LOGIC
CLK
fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
tSIR
tHIR
相關PDF資料 |
PDF描述 |
|---|---|
| MACH120-12 | High-Performance EE CMOS Programmable Logic |
| MACH131SP-12YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-15YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-5YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-7YC | High-Performance EE CMOS Programmable Logic |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MACH120-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: |
| MACH120-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH130-15 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH130-15JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH130-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: |
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