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參數(shù)資料
| 型號： | MACH131SP-7VC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 7.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 47/48頁 |
| 文件大小： | 1136K |
| 代理商： | MACH131SP-7VC |
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8
MACH 1 & 2 Families
The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,
and to the I/O cell. The feedback is always available regardless of the conguration of the I/O cell.
This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as
inputs if not needed as outputs. The basic output macrocell congurations are shown in Figure 4.
The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried
macrocell is provided only as an internal feedback signal which feeds the switch matrix. This
allows the designer to generate additional logic without requiring additional pins. The buried
macrocell can also be used to register or latch inputs. The input register is a D-type ip-op; the
input latch is a transparent-low D-type latch. Once congured as a registered or latched input, the
buried macrocell cannot generate logic from the product-term array. The basic buried macrocell
congurations are shown in Figure 6.
Figure 3. Output Macrocell
Note:
1. Latch option available on MACH 2 devices only.
CLK0
CLKn
1
0
1
0
AR
AP
Q
D/T/L1
To
Switch
Matrix
Sum of Products
from Logic
Allocator
PAL-Block
Asynchronous
Preset
To I/O
Cell
PAL-Block
Asynchronous
Reset
14051K-004
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH131SP-7YI | High-Performance EE CMOS Programmable Logic |
| MACH120-12JC | High-Performance EE CMOS Programmable Logic |
| MACH120-15JC | High-Performance EE CMOS Programmable Logic |
| MACH120-12 | High-Performance EE CMOS Programmable Logic |
| MACH131SP-12YC | High-Performance EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH131SP-7YC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH131SP-7YI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF EE CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| MACH210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:44 pin QFP socket/28 pin DIP 0.6” plug |
| MACH210-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH21012JC | 制造商:AMD 功能描述:* |
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