參數(shù)資料
型號(hào)： MACH131SP-7YI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： High-Performance EE CMOS Programmable Logic
中文描述： EE PLD, 5.5 ns, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 4/48頁(yè)
文件大?。?/td> 1136K
代理商： MACH131SP-7YI
12
MACH 1 & 2 Families
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed xed speed. The design of the switch
matrix and PAL blocks guarantee a xed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
VCC
01
11
10
00
Output Enable
Product Terms
(Common to bank of
I/O Cells)
From Output
Macrocell
To Switch
Matrix
To Buried
Macrocell
(MACH 2 only)
Figure 7. I/O Cell
14051K-007
SpeedLocking
Shared Expander Delay
Non-MACH
5 PT
10 PT
15 PT
tPD (ns)
7.4 ns
10.4 ns
MACH 1 & 2
8.8 ns
6.6 ns
5 ns
11
10
9
8
7
6
5
5.8 ns
Product Terms
Parallel Expander Delay
Patented Architecture
Path Independent
Logic/Routing Independent
Guaranteed Fixed Timing
Up to 16 Product Terms per Output
Variable
Path Dependent
Logic/Routing Dependent Delays
Unpredictable
4-5 Product Terms before Delays
Non-MACH
MACH 1 & 2 SpeedLocking
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
14051K-001
相關(guān)PDF資料
PDF描述
MACH120-12JC High-Performance EE CMOS Programmable Logic
MACH120-15JC High-Performance EE CMOS Programmable Logic
MACH120-12 High-Performance EE CMOS Programmable Logic
MACH131SP-12YC High-Performance EE CMOS Programmable Logic
MACH131SP-15YC High-Performance EE CMOS Programmable Logic
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MACH210-12 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic
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MACH210-12JI 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic
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