參數(shù)資料
型號： MACH210A-10JC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Density EE CMOS Programmable Logic
中文描述： EE PLD, 10 ns, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 26/47頁
文件大?。?/td> 347K
代理商： MACH210A-10JC
MACH210AQ-18/24 (Ind)
32
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25
°C,
6
pF
COUT
Output Capacitance
VOUT= 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
18
24
ns
(Note 3)
D-type
16
20.5
ns
T-type
17
22
ns
tH
Register Data Hold Time
0
ns
tCO
Clock to Output (Note 3)
8.5
10
ns
tWL
Clock
LOW
7.5
10
ns
tWH
Width
HIGH
7.5
10
ns
D-type
40
32
MHz
T-type
38
30.5
MHz
fMAX
D-type
47
36
MHz
T-type
44
34.5
MHz
D-type
61.5
47
MHz
T-type
57
47
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
16
20.5
ns
tHL
Latch Data Hold Time
0
ns
tGO
Gate to Output (Note 3)
10
ns
tGWL
Gate Width LOW
7.5
10
ns
tPDL
Input, I/O, or Feedback to Output Through
20.5
26.5
ns
Transparent Input or Output Latch
tSIR
Input Register Setup Time
2.5
ns
tHIR
Input Register Hold Time
3.5
4
ns
tICO
Input Register Clock to Combinatorial Output
22
28
ns
tICS
Input Register Clock to Output Register Setup
20.5
26.5
ns
22
28
ns
tWICL
Input Register
LOW
7.5
10
ns
tWICH
Clock Width
HIGH
7.5
10
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL+ tWICH)
66.5
50
MHz
tSIL
Input Latch Setup Time
2.5
ns
tHIL
Input Latch Hold Time
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
24
30
ns
tIGOL
Input Latch Gate to Output Through Transparent
26.5
32.5
ns
Output Latch
tSLL
Setup Time from Input, I/O, or Feedback Through
18
23
ns
Transparent Input Latch to Output Latch Gate
tIGS
Input Latch Gate to Output Latch Setup
22
28
ns
tWIGL
Input Latch Gate Width LOW
7.5
10
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
23
29
ns
Input and Output Latches
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
1/(tS + tH)
-18
-24
D-type
T-type
tS
相關(guān)PDF資料
PDF描述
MACH210A-10VC High-Density EE CMOS Programmable Logic
MACH210A-12JC High-Density EE CMOS Programmable Logic
MACH210A-12VC High-Density EE CMOS Programmable Logic
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MACH210A-10VC 制造商:Rochester Electronics LLC 功能描述:- Bulk
MACH210A-12 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic
MACH210A-12JC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic
MACH210A-12JI 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic
MACH210A-12VC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic
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