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參數(shù)資料
| 型號(hào)： | MACH210A-12JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 16/47頁(yè) |
| 文件大?。?/td> | 347K |
| 代理商： | MACH210A-12JC |
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23
MACH210-14/18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25
°C,
6
pF
COUT
Output Capacitance
VOUT= 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
14.5
18
24
ns
(Note 3)
D-type
8.5
12
16
ns
T-type
10
13.5
17
ns
tH
Register Data Hold Time
0
ns
tCO
Clock to Output (Note 3)
10
12
14.5
ns
tWL
Clock
LOW
7.5
10
ns
tWH
Width
HIGH
7.5
10
ns
D-type
53
40
32
MHz
T-type
50
38
30.5
MHz
fMAX
D-type
61.5
53
38
MHz
T-type
57
44
34.5
MHz
66.5
50
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
8.5
12
16
ns
tHL
Latch Data Hold Time
0
ns
tGO
Gate to Output (Note 3)
12
13.5
14.5
ns
tGWL
Gate Width LOW
7.5
10
ns
tPDL
Input, I/O, or Feedback to Output Through
17
20.5
26.5
ns
Transparent Input or Output Latch
tSIR
Input Register Setup Time
2.5
ns
tHIR
Input Register Hold Time
3
3.5
4
ns
tICO
Input Register Clock to Combinatorial Output
18
22
28
ns
tICS
Input Register Clock to Output Register Setup
14.5
18
24
ns
16
19.5
25.5
ns
tWICL
Input Register
LOW
7.5
10
ns
tWICH
Clock Width
HIGH
7.5
10
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL+ tWICH)
66.5
50
MHz
tSIL
Input Latch Setup Time
2.5
ns
tHIL
Input Latch Hold Time
3
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
20.5
24
30
ns
tIGOL
Input Latch Gate to Output Through Transparent
23
26.5
32.5
ns
Output Latch
tSLL
Setup Time from Input, I/O, or Feedback Through
11
14.5
18
ns
Transparent Input Latch to Output Latch Gate
tIGS
Input Latch Gate to Output Latch Setup
16
19.5
25.5
ns
tWIGL
Input Latch Gate Width LOW
7.5
10
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
19.5
23
29
ns
Input and Output Latches
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
1/(tWL + tWH)
-18
-24
D-type
T-type
tS
-14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
| MACH210A-7 | High-Density EE CMOS Programmable Logic |
| MACH215-12JC | High-Density EE CMOS Programmable Logic |
| MACH215-15JC | High-Density EE CMOS Programmable Logic |
| MACH215-12 | High-Density EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH210A-12JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-14JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-18JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH210A-24JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
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