參數(shù)資料
型號(hào)： MAS31753FXXXX
廠商： DYNEX SEMICONDUCTOR LTD
元件分類： DMA控制器
英文描述： 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
封裝： QFP-84
文件頁(yè)數(shù)： 1/31頁(yè)
文件大小： 238K
代理商： MAS31753FXXXX
MA31753
1/31
AS[0:3]
PS[0:3]
PB[0:3]
D[0:16]
A[0:15]
CSN
CLK
RESETN
DSN
AS
MION
OIN
RDWN
RDN
WRN
RDYN
GRANTN
REQN
LOCKN
DMAKN
DREQN[0:3]
DACKN[0:3]
DMAE
SEC/FIRSTN
DONEN
AKRDN
AKWRN
EXADEN
PEN
MPROEN
INTRN
REQINN
GEINN
GEOUTN
DPARN
DTON
VDD
VSS
MA31753
DMAC
The MA31753 Direct Memory Access Controller (DMAC) is
a peripheral interface circuit design primarily for use with the
MA31750 microprocessor. Each DMAC provides up to four
independant, prioritised channels each of which can perform
DMA transfers between memory and/or I/O devices using the
MA31750 bus. Each channel has its own programmable
internal priority and can be masked under program control.
Further, individual channels have their own associated status
and control words enabling an individual channel to be re-
programmed without disturbing transfers which may be taking
place on other channels. Three basic transfer modes are
available:
Direct Memory to I/O peripheral transfers,
Direct I/O to Memory transfers,
Memory to Memory transfers,
I/O to I/O transfers.
The MA31753 interfaces directly to the MA31750 bus,
directly supporting on chip parity generation and supporting
expanded memory via an MA31751 MMU with either 1 MWord
(1750A mode) or 16MWords (1750B mode) of logical memory.
The MA31753 uses System memory to hold address and
count information for each transfer. Once this information has
been prepared by the processor the DMAC can conduct a
number of transfers without further processor intervention.
FEATURES
s Radiation Hard CMOS SOS Technology
s Four Independant DMA Channels
s MIL-STD-1750A or B Operation in an MA31750 System
s Capable of Processor Independant Table Driven
Operation
s Memory to Memory, I/O to Memory, Memory to I/O and
I/O to I/O Transfers Supported
s Masking of Individual Channel DMA Requests
s Simple MA31750 Bus Interface
s Single Word, Double Word or Multi-Word Transfers for
each of the DMA Channels
s Cascade Interface Allows for Channel Expansion
s Programmable Channel Priority
s Parity Checking Available
Figure 1: Pin Connections - Top View
MA31753
DMA Controller (DMAC) For An MA31750 System
Replaces January 2000 version, DS3825-5.0
DS3825-5.1 July 2002
相關(guān)PDF資料
PDF描述
MAR28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
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MAS28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
MAH28155LXXXX 24 I/O, PIA-GENERAL PURPOSE, CQCC44
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