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參數(shù)資料
| 型號： | MAX038CWP |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GEN WAVEFORM HI-FREQ 20-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 36 |
| 頻率： | 0.1Hz ~ 20MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 45mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | Q1136045 |
With FADJ disabled, the output frequency can still be
changed by modulating IIN.
Swept Frequency Operation
The output frequency can be swept by applying a vary-
ing signal to IIN or FADJ. IIN has a wider range, slightly
slower response, lower temperature coefficient, and
requires a single polarity current source. FADJ may be
used when the swept range is less than ±70% of the
center frequency, and it is suitable for phase-locked
loops and other low-deviation, high-accuracy closed-
loop controls. It uses a sweeping voltage symmetrical
about ground.
Connecting a resistive network between REF, the volt-
age source, and FADJ or IIN is a convenient means of
offsetting the sweep voltage.
Duty Cycle
The voltage on DADJ controls the waveform duty cycle
(defined as the percentage of time that the output
waveform is positive). Normally, VDADJ = 0V, and the
duty cycle is 50% (Figure 2). Varying this voltage from
+2.3V to -2.3V causes the output duty cycle to vary
from 15% to 85%, about -15% per volt. Voltages
beyond ±2.3V can shift the output frequency and/or
cause instability.
DADJ can be used to reduce the sine-wave distortion.
The unadjusted duty cycle (VDADJ = 0V) is 50% ±2%;
any deviation from exactly 50% causes even order har-
monics to be generated. By applying a small
adjustable voltage (typically less than ±100mV) to
VDADJ, exact symmetry can be attained and the distor-
tion can be minimized (see Figure 2).
The voltage on DADJ needed to produce a specific
duty cycle is given by the formula:
VDADJ = (50% - dc) x 0.0575
[11]
or:
VDADJ = (0.5 - [tON ÷to]) x 5.75
[12]
where:
VDADJ = DADJ voltage (observe the polarity)
dc = duty cycle (in %)
tON = ON (positive) time
to = waveform period.
Conversely, if VDADJ is known, the duty cycle and ON
time are given by:
dc = 50% - (VDADJ x 17.4)
[13]
tON = to x (0.5 - [VDADJ x 0.174])
[14]
High-Frequency Waveform Generator
MAX038
1
μF
GND
COSC
12
AO
V-
18
11
9
2
6
GND GND
5
8
10
7
1
13
14
15
16
N.C.
3
FADJ
IIN
DADJ
REF
OUT
DV+
DGND
SYNC
PDI
PDO
V+ A1
4
17
20
–5V +5V
C2
1nF
C3
1
μF
C1
12k
Ω
R1
20k
Ω
RIN
FREQUENCY
50
Ω
R2
N.C.
CF
19
SINE-WAVE
OUTPUT
2 x 2.5V
RIN x CF
Fo =
MAX038
100k
Ω
R5
5k
Ω
R6
100k
Ω
R7
100k
Ω
R3
100k
Ω
R4
DADJ
REF
+2.5V
–2.5V
PRECISION DUTY-CYCLE ADJUSTMENT CIRCUIT
ADJUST R6 FOR MINIMUM SINE-WAVE DISTORTION
Figure 2. Operating Circuit with Sine-Wave Output and 50% Duty Cycle; SYNC and FADJ Disabled
MAX038
Maxim Integrated
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX038CWP+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX038CWP+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX038CWP-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX038EPP | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:High-Frequency Waveform Generator |
| MAX038EVKIT | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Evaluation Kit for the MAX038 |
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