參數(shù)資料
型號(hào): MAX1021BETX+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 29/40頁(yè)
文件大?。?/td> 0K
描述: IC ADC/DAC 10BIT W/FIFO 36-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: ADC,DAC
分辨率(位): 10 b
采樣率(每秒): 300k
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 2.7V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-TQFN 裸露焊盤(6x6)
包裝: 帶卷 (TR)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
35
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware
LDAC command DAC-
register update. For a software-command DAC-register
update, tS is valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.
LDAC Functionality
Drive
LDAC low to transfer the content of the input
registers to the DAC registers. Drive
LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2s. See Figure 14.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run dig-
ital lines underneath the MAX1021/MAX1043
package. High-frequency noise in the AVDD power
supply may affect performance. Bypass the AVDD sup-
ply with a 0.1F capacitor to AGND, close to the AVDD
pin. Bypass the DVDD supply with a 0.1F capacitor to
DGND, close to the DVDD pin. Minimize capacitor lead
lengths for best supply-noise rejection. If the power
supply is very noisy, connect a 10Ω resistor in series
with the supply to improve power-supply filtering.
The MAX1021/MAX1043 thin QFN packages contain an
exposed pad on the underside of the device. Connect
this exposed pad to AGND. Refer to the
MAX1258 EV kit
for an example of proper layout.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1021/MAX1043 is measured using the end-
point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
SCLK
DOUT
X = DON'T CARE.
MSB1
LSB1
MSB2
(ACQUISITION1)
(ACQUISITION2)
(CONVERSION1)
DIN
(CONVERSION BYTE)
CS
EOC
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion Without
CNVST
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MAX1022BETX+T 功能描述:ADC / DAC多通道 10Bit AD/DACs w/FIFO Temp Sns/GPIO Ports RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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