8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 14-Bit ADCs 15 Maxim Integrated A" />
參數(shù)資料
型號(hào)： MAX1033EUP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/32頁(yè)
文件大小： 0K
描述： IC ADC 14BIT SER 115KSPS 20TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 14
采樣率（每秒）： 115k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 879mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；4 個(gè)單端，雙極；2 個(gè)差分，單極；2 個(gè)差分，雙極
MAX1032/MAX1033
8- and 4-Channel, ±3 x VREF
Multirange Inputs, Serial 14-Bit ADCs
15
Maxim Integrated
As a result, the analog input impedance is relatively
constant over input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel. For
example, to configure CH2 and CH3 for a ±3 x VREF dif-
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±3 x VREF range
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1032/MAX1033 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD
and -SFDR vs. Input Frequency plot in the
Typical
Operating Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-
ended analog input voltage range that produces a valid
digital output. Each analog input channel can be inde-
pendently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DIN
S
C2
C1
C0
0
**
ANALOG INPUT
TRACK AND HOLD*
DOUT
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
BYTE 1
BYTE 2
BYTE 3
BYTE 4
SSTRB
HOLD
TRACK
HOLD
HIGH
IMPEDANCE
HIGH
IMPEDANCE
tACQ
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
fSAMPLE
≈ fSCLK / 32
SAMPLING INSTANT
**DIN BYTES 2 TO 4 MUST BE DRIVEN TO LOGIC 0 TO OBTAIN A VALID CONVERSION.
Figure 2. External Clock-Mode Conversion (Mode 0)
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