參數(shù)資料
型號： MAX1058BETM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 42/44頁
文件大小： 0K
描述： IC ADC/DAC 10BIT 48-TQFN-EP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
類型： ADC，DAC
分辨率（位）： 10 b
采樣率（每秒）： 225k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應商設備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1057), external reference VREF = 2.5V (MAX1057), VAVDD = VDVDD = 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1057), VAVDD = VDVDD = 5V
(MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1057, VAVDD = 2.7V to
±0.06
±0.5
ADC Positive-Supply Rejection
PSRA
Full-
scale
input
MAX1020/MAX1022/MAX1058,
VAVDD = 4.75V to 5.25V
±0.06
±0.5
mV
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
tCP
40
ns
SCLK Pulse-Width High
tCH
40/60 duty cycle
16
ns
SCLK Pulse-Width Low
tCL
60/40 duty cycle
16
ns
GPIO Output Rise/Fall After
CS Rise
tGOD
CLOAD = 20pF
100
ns
GPIO Input Setup Before
CS Fall
tGSU
0ns
LDAC Pulse Width
tLDACPWL
20
ns
CLOAD = 20pF, SLOW = 0
1.8
12.0
SCLK Fall to DOUT Transition
(Note 16)
tDOT
CLOAD = 20pF, SLOW = 1
10
40
ns
CLOAD = 20pF, SLOW = 0
1.8
12.0
SCLK Rise to DOUT Transition
(Notes 16, 17)
tDOT
CLOAD = 20pF, SLOW = 1
10
40
ns
CS Fall to SCLK Fall Setup Time
tCSS
10
ns
SCLK Fall to
CS Rise Setup TimetCSH
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
0
2000
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
25
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
1.5
25.0
ns
EOC Fall to CS Fall
tRDS
30
ns
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
CKSEL = 01 (voltage conversion)
9
CKSEL = 10 (voltage conversion),
internal reference on
9
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
tDOV
CKSEL = 10 (voltage conversion),
internal reference initially off
80
s
CKSEL = 00, CKSEL = 01 (temp sense)
40
ns
CNVST Pulse Width
tCSW
CKSEL = 01 (voltage conversion)
1.4
s
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