input to VDD
參數(shù)資料
型號(hào): MAX1063AEEG+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/20頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 250KSPS 24-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
位數(shù): 10
采樣率(每秒): 250k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 762mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極;4 個(gè)單端,雙極;2 個(gè)偽差分,單極;2 個(gè)偽差分,雙極
MAX1061/MAX1063
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within (GND - 300mV) to (VDD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/Hold
The MAX1061/MAX1063 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this occurs approximately 1s after writing the
control byte. In single-ended operation, IN- is connect-
ed to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative input (-), and the difference of (IN+) - (IN-) is
sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ = 7(RS + RIN)CIN
where RS is the source impedance of the input signal,
RIN (800) is the input resistance, and CIN (12pF) is
the ADC’s input capacitance. Source impedances
below 3k have no significant impact on the MAX1061/
MAX1063s’ AC performance.
Higher source impedances can be used if a 0.01F
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1061/MAX1063 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADC's sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-alias filtering is recom-
mended.
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1061/MAX1063 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
10
______________________________________________________________________________________
CH0
CH2
CH1
CH3
CH4
CH6
CH7
CH5
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800
CHOLD
12pF
HOLD
10-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR
+
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3a. MAX1061 Simplified Input Structure
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800
CHOLD
12pF
HOLD
ZERO
COMPARATOR
+
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1 AND CH2/CH3
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
10-BIT CAPACITIVE DAC
REF
Figure 3b. MAX1063 Simplified Input Structure
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MAX1063AEEG+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 3V 10Bit 4Ch 400ksps w/2.5V Ref & Prl Int RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1063AEEG+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 3V 10Bit 4Ch 400ksps w/2.5V Ref & Prl Int RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1063AEEG-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1063BCEG 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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