參數(shù)資料
        型號(hào): MAX11049ECB+T
        廠商: Maxim Integrated Products
        文件頁(yè)數(shù): 8/25頁(yè)
        文件大?。?/td> 0K
        描述: IC ADC 16BIT PAR 250KSPS 64TQFP
        標(biāo)準(zhǔn)包裝: 750
        位數(shù): 16
        采樣率(每秒): 250k
        數(shù)據(jù)接口: 并聯(lián)
        轉(zhuǎn)換器數(shù)目: 8
        功率耗散(最大): 3.48W
        電壓電源: 模擬和數(shù)字
        工作溫度: -40°C ~ 85°C
        安裝類型: *
        封裝/外殼: *
        供應(yīng)商設(shè)備封裝: *
        包裝: *
        輸入數(shù)目和類型: 8 個(gè)單端,單極
        MAX11047–MAX11049/MAX11057–MAX11059
        4-/6-/8-Channel, 16-/14-Bit,
        Simultaneous-Sampling ADCs
        16
        ______________________________________________________________________________________
        Figures 2 and 3 illustrate the clamp circuit voltage-cur-
        rent characteristics for a source impedance RS =
        1280
        . While the input voltage is within the -300mV to
        +(VAVDD + 300mV) range, no current flows in the input
        clamps. Once the input voltage goes beyond this volt-
        age range, the clamps turn on and limit the voltage at
        the input pin.
        Applications Information
        Digital Interface
        The bidirectional, parallel, digital interface, CR0–CR3,
        sets the 4-bit configuration register. This interface
        configures the following control signals: chip select
        (CS), read (RD), write (WR), end of conversion (EOC),
        and convert start (CONVST). Figures 6 and 7 and the
        Timing Characteristics in the
        Electrical Characteristics
        table show the operation of the interface.
        DB0–DB15/13, output the 16-/14-bit conversion result.
        All bits are high impedance when RD = 1 or CS = 1.
        CR3 (Int/Ext Reference)
        CR3 selects the internal or external reference. The POR
        default = 0.
        0 = internal reference, REFIO internally driven through a
        10k
        resistor, bypass with 0.1F capacitor to AGND.
        1 = external reference, drive REFIO with a high quality
        reference.
        CR2 (Output Data Format)
        CR2 selects the output data format. The POR default = 0.
        0 = offset binary.
        1 = two’s complement.
        CR1 (Reserved)
        CR1 must be set to 0.
        CR0 (CONVST Mode)
        CR0 selects the acquisition mode. The POR default = 0.
        0 = CONVST controls the acquisition and conversion.
        Drive CONVST low to start acquisition. The rising edge
        of CONVST begins the conversion.
        1 = acquisition mode starts as soon as previous con-
        version is complete. The rising edge of CONVST begins
        the conversion.
        Programming the Configuration Register
        To program the configuration register, bring the CS and
        WR low and apply the required configuration data on
        CR3–CR0 of the bus and then raise WR once to save
        changes.
        CAUTION: The host driving CR3–CR0 must relin-
        quish the bus when the conversion results of the
        ADC are being read.
        Starting a Conversion
        CONVST initiates conversions. The devices provide two
        acquisition modes set through the configuration regis-
        ter. Allow a quiet time (tQ) of 500ns prior to the start of
        conversion to avoid any noise interference during read-
        out or write operations from corrupting a sample.
        CR3
        CR2
        CR1
        CR0
        Int/Ext
        Reference
        Output
        Data Format
        Must be set
        to 0
        CONVST
        Mode
        Table 1. Configuration Register
        SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
        I CLAMP
        (mA)
        30
        20
        0
        10
        -10
        -20
        -15
        -10
        -5
        0
        5
        10
        15
        20
        25
        -25
        -30
        40
        RS = 1170
        I
        VAVDD = 5.0V
        AT SOURCE
        AT CH_ INPUT
        Figure 2. Input Clamp Characteristics
        SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
        6
        4
        2
        0
        -2
        -4
        8
        I CLAMP
        (mA)
        -20
        -15
        -10
        -5
        10
        15
        20
        25
        -25
        0
        5
        RS = 1170
        I
        VAVDD = 5.0V
        AT CH_ INPUT
        AT SOURCE
        Figure 3. Input Clamp Characteristics (Zoom In)
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