參數(shù)資料
型號： MAX11060GUU+T
廠商： Maxim Integrated Products
文件頁數(shù)： 22/35頁
文件大?。?/td> 0K
描述： IC ADC 16BIT DELTA SIGMA 38TSSOP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 3.07M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.1W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 106°C
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應商設(shè)備封裝： 38-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，雙極；4 個差分，雙極
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
29
Maxim Integrated
Referring back to the analog input, since the entire sam-
pling section of the converter also paused for two clock
cycles, the sampling point for sample 5 is also paused
by two clock cycles, possibly creating a small distur-
bance at the SYNC falling edge. This disturbance is fil-
tered with the digital filter, which makes it less distinct.
If the SYNC falling edge occurred during the same XIN
clock period as the DRDYOUT signal, the disturbance
does not affect the periodic timing since the SYNC
falling edge would demand a pause of zero XIN clock
cycles. Hence, connecting the DRDYOUT of the last
converter to the SYNC inputs of many converters, as
illustrated in Figure 13, aligns the sampling of the con-
verters on the first SYNC falling edge, but does not dis-
turb a regular sampling process for future samples.
See the
Multiple Device Synchronization section for dif-
ferent ways to use the SYNC input.
Transfer Function
Figures 17 shows the bipolar I/O transfer function.
Code transitions occur halfway between successive-
integer LSB values. Output coding is binary, with 1 LSB
= (0.88 x VREFIO) x 2/524,288 in 19-bit mode, (0.88 x
VREFIO) x 2/16,777,216 in 24-bit mode, and (0.88 x
VREFIO) x 2/65536 for the MAX11060.
Power-On Reset
The serial interface, logic, digital filter, and modulator
circuits reset to zero at power-up. The power-on reset
circuit releases this reset no more than 1ms after
VDVDD rises above 2V.
OUTPUT CODE
DIFFERENTIAL INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
0
-FS
FULL-SCALE
TRANSITION
*N = 19 FOR 19-BIT TRANSFER
FUNCTION,
N = 24 FOR 24-BIT TRANSFER
FUNCTION
FS = +0.88 x VREFIO
ZS = 0
-FS = -0.88 x VREFIO
1 LSB =
2(0.88 x VREFIO)
2N*
100...001
100...000
111...110
000...010
011...111
011..110
000...011
000...001
000...000
111...111
N = 16 FOR MAX11060
Figure 17. ADC Transfer Function
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