參數(shù)資料
型號(hào): MAX11101EWC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 19/19頁(yè)
文件大小: 0K
描述: IC ADC 14BIT SRL 200KSPS 12WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.3W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 12-WLP
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 1 個(gè)單端,單極
其它名稱: MAX11101EWC+TDKR
Maxim Integrated Products 9
MAX11101
14-Bit, +5V, 200ksps ADC with 10A Shutdown
Detailed Description
The MAX11101 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 14-bit output.
Figure 4 shows the MAX11101 in its simplest configura-
tion. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (FPs).
The MAX11101 has two power modes: normal and shut-
down. Driving CS high places the MAX11101 in shut-
down, reducing the supply current to 0.1FA (typ), while
pulling CS low places the MAX11101 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
Analog Input
Figure 5 illustrates the input sampling architecture of the
ADC. The voltage applied at REF sets the full-scale input
voltage.
Track-and-Hold (T/H)
In track mode, the analog signal is acquired on the inter-
nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
Figure 3. Detailed Serial Interface Timing
DOUT
a) VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
DOUT
1mA
DGND
CLOAD = 50pF
VDD
DOUT
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
DOUT
1mA
DGND
CLOAD = 50pF
VDD
SCLK
DOUT
tCSS
tCH
tCL
tDV
tCSH
tCSW
tTR
tDO
tCP
CS
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