參數(shù)資料
型號(hào): MAX11102AUB+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/30頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT SPI/SRL 10UMAX-EP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 2M
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 707.3mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 10-µMAX-EP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,單極
12
Maxim Integrated
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
MAX11102/03/05/06/10/11/15/16/17
ELECTRICAL CHARACTERISTICS (MAX11111) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, CS)
Digital Input High Voltage
VIH
0.75 x
VOVDD
V
Digital Input Low Voltage
VIL
0.25 x
VOVDD
V
Digital Input Hysteresis
VHYST
0.15 x
VOVDD
V
Digital Input Leakage Current
IIL
Inputs at GND or VDD
0.001
Q
1
F
A
Digital Input Capacitance
CIN
2
pF
DIGITAL OUTPUT (DOUT)
Output High Voltage
VOH
ISOURCE = 200A (Note 2)
0.85 x
VOVDD
V
Output Low Voltage
VOL
ISINK = 200A (Note 2)
0.15 x
VOVDD
V
High-Impedance Leakage
Current
IOL
Q
1.0
F
A
High-Impedance Output
Capacitance
COUT
4
pF
POWER SUPPLY
Positive Supply Voltage
VDD
2.2
3.6
V
Digital I/O Supply Voltage
VOVDD
1.5
VDD
V
Positive Supply Current
(Full-Power Mode)
IVDD
VAIN_ = VGND
3.3
mA
IOVDD
VAIN_ = VGND
0.33
Positive Supply Current
(Full-Power Mode), No Clock
IVDD
1.98
mA
Power-Down Current
IPD
Leakage only
1.3
10
F
A
Line Rejection
VDD = +2.2V to +3.6V, VREF = 2.2V
0.17
LSB/V
TIMING CHARACTERISTICS (Note 1)
Quiet Time
tQ
(Note 2)
4
ns
CS Pulse Width
t1
(Note 2)
10
ns
CS Fall to SCLK Setup
t2
(Note 2)
5
ns
CS Falling Until DOUT High-
Impedance Disabled
t3
(Note 2)
1
ns
Data Access Time After SCLK
Falling Edge (Figure 2)
t4
VOVDD = 2.2V - 3.6V
15
ns
VOVDD = 1.5V - 2.2V
16.5
SCLK Pulse Width Low
t5
Percentage of clock period (Note 2)
40
60
%
SCLK Pulse Width High
t6
Percentage of clock period (Note 2)
40
60
%
Data Hold Time From SCLK
Falling Edge
t7
Figure 3
5
ns
SCLK Falling Until DOUT High-
Impedance
t8
Figure 4 (Note 2)
2.5
14
ns
Power-Up Time
Conversion cycle (Note 2)
1
Cycle
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