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參數(shù)資料
| 型號(hào)： | MAX11208AEUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 19BIT SRL 120SPS 10UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 19 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 444mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
10_ _ ______________________________________________________________________________________
MAX11208
20-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADC with 2-Wire Serial Interface
The RDY/DOUT is used to signal data ready, as well as
reading the data out when SCLK pulses are applied.
RDY/DOUT is high by default. The MAX11208 pulls RDY/
DOUT low when data is available at the end of conver-
sion, and stays low until clock pulses are applied at SCLK
input; on applying the clock pulses at SCLK, the RDY/
DOUT outputs the conversion data on every SCLK posi-
tive edge. To monitor data availability, pull RDY/DOUT
high after reading the 20 bits of data by supplying a 25th
SCLK pulse. The different operational modes using this
2-wire interface are described in the following sections.
Data Read Following Every Conversion
The MAX11208 indicates conversion data availability,
as well as lets the retrieval of data through the RDY/
DOUT output. The RDY/DOUT output idles at the value
of the last bit read unless a 25th SCLK pulse is provided,
causing RDY/DOUT to idle high. RDY/DOUT is pulled low
when the conversion data is available.
The timing diagram for the data read is shown in Figure
1. Once a low is detected on RDY/DOUT, clock pulses
at SCLK clock out the data. Data is shifted out MSB first
and is in binary two’s complement format. Once all the
data has been shifted out, a 25th SCLK is required to
pull the RDY/DOUT output back to the idle high state.
See Figure 2.
If the data is not read before the next conversion data is
updated, the old data is lost, as the new data overwrites
the old value.
Data Read Followed by Self-Calibration
To initiate self-calibration at the end of a data read,
provide a 26th SCLK pulse. After reading the 24 bits of
conversion data, a 25th positive edge on SCLK pulls the
RDY/DOUT output back high, indicating the end of data
read. Provide a 26th SCLK pulse to initiate a self-calibra-
tion routine starting on the falling edge of the 26th SCLK.
A subsequent falling edge of RDY/DOUT indicates data
availability at the end of calibration. The timing is illus-
trated in Figure 3.
Data Read Followed by Sleep Mode
The MAX11208 can be put into sleep mode to save
power between conversions. To activate the sleep mode,
idle the SCLK high any time after the RDY/DOUT output
goes low (that is, after conversion data is available). It is
not required to read out all 20 bits before putting the part
in sleep mode. Sleep mode is activated after the SCLK is
held high (see Figure 4). The RDY/DOUT output is pulled
high once the device enters sleep mode. To come out
of the sleep mode, pull SCLK low. After the sleep mode
is deactivated (when the device wakes up), conversion
starts again and RDY/DOUT goes low indicating the next
conversion data is available. See Figure 4.
Single Conversion Mode
For operating the MAX11208 in single conversion mode,
activate and deactivate sleep mode between conver-
sions (as described in the Data Read Followed by Sleep
Mode section). Single conversion mode reduces power
consumption by shutting down the device when idle
between conversions. See Figure 4.
Single Conversion Mode with
Self-Calibration at Wakeup
The MAX11208 can be put in self-calibration mode imme-
diately after wake-up from sleep mode. Self-calibration at
wake-up helps to compensate for temperature or supply
changes if the device is shut down for extensive periods.
To automatically start self-calibration at the end of sleep
mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th
SCLK, keep it high for as long as shutdown is desired.
Once SCLK is pulled back low, the device automatically
performs a self-calibration, and when the data is ready,
the RDY/DOUT output goes low. See Figure 5. This also
achieves the purpose of single conversions with self-
calibration.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11208BEUB+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11208BEUB+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11209 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:18-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO |
| MAX11209EEE | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:The MAX11200, MAX11206, MAX11209, MAX11210, and MAX11213 evaluation kits (EV kits) consist of one MAX11200, MAX11206, MAX11209, MAX11210, or MAX11213 evaluation board and software. |
| MAX11209EEE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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