參數(shù)資料
型號： MAX11209EEE+T
廠商： Maxim Integrated Products
文件頁數(shù)： 22/27頁
文件大?。?/td> 0K
描述： ADC 18BIT DELT-SIG PROGR 16-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 18
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 667mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： *
4
Maxim Integrated
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11209/MAX11211
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.)
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
lower or continuous data rate of 60sps/50sps.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply
VAVDD
2.7
3.6
V
Digital Supply
VDVDD
1.7
3.6
V
Total Operating Current
AVDD + DVDD
Buffers disabled
235
300
F
A
Buffers enabled
255
AVDD Sleep Current
0.15
2
F
A
AVDD Operating Current
Buffers disabled
185
235
F
A
Buffers enabled
205
DVDD Sleep Current
0.25
2
F
A
DVDD Operating Current
50
65
F
A
SPI TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
5
MHz
SCLK Clock Period
tCP
200
ns
SCLK Pulse-Width High
tCH
80
ns
SCLK Pulse-Width Low
tCL
60% duty cycle at 5MHz
80
ns
CS Low to 1st SCLK Rise Setup
tCSS0
40
ns
CS High to 17th SCLK Setup
tCSS1
40
ns
CS High After 16th SCLK
Falling Edge Hold
tCSH1
3
ns
CS Pulse-Width High
tCSW
40
ns
DIN to SCLK Setup
tDS
40
ns
DIN Hold After SCLK
tDH
0
ns
RDY/DOUT Transition Valid After
SCLK Fall
tDOT
Output transition time, data changes on
falling edge of SCLK
40
ns
RDY/DOUT Remains Valid After
SCLK Fall
tDOH
Output hold time allows for negative edge
data read
3
ns
RDY/DOUT Valid Before SCLK Rise
tDOL
tDOL = tCL - tDOT
40
ns
CS Rise to RDY/DOUT Disable
tDOD
CLOAD = 20pF
25
ns
CS Fall to RDY/DOUT Valid
tDOE
Default value of RDY is 1 for minimum
specification; maximum specification for
valid 0 on RDY/DOUT
0
40
ns
DATA Fetch
tDF
Maximum time after RDY asserts to read
DATA register; tCNV is the time for one
conversion
0
tCNV -
60 x tCP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX11209EVKIT+ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVKIT for the MAX11209 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
MAX1121 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:1.8V, 12-Bit, 170Msps ADC for Broadband Applications
MAX11210 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO
MAX11210EEE 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:The MAX11200, MAX11206, MAX11209, MAX11210, and MAX11213 evaluation kits (EV kits) consist of one MAX11200, MAX11206, MAX11209, MAX11210, or MAX11213 evaluation board and software.
MAX11210EEE+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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