參數(shù)資料
型號(hào): MAX1142ACAP+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 19/20頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 200KSPS 20-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 640mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
MAX1142/MAX1143
14-Bit ADC, 200ksps, +5V Single-Supply
with Reference
8
_______________________________________________________________________________________
PIN
NAME
FUNCTION
1
REF
Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AVDD. Bypass to
AGND with a 2.2F capacitor when using the internal reference.
2
REFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22F. When using an
external reference, connect REFADJ to AVDD to disable the internal bandgap reference.
3
AGND
Analog Ground. This is the primary analog ground (Star Ground).
4
AVDD
Analog Supply 5V
±5%. Bypass AVDD to AGND (pin 3) with a 0.1F capacitor.
5
DGND
Digital Ground
6
SHDN
Shutdown Control Input. Drive
SHDN low to put the ADC in shutdown mode.
7
P2
User-Programmable Output 2
8
P1
User-Programmable Output 1
9
P0
User-Programmable Output 0
10
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period
before the MSB decision. It is high impedance when
CS is high in external clock mode.
11
DOUT
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
12
RST
Reset Input. Drive
RST low to put the device in the power-on default mode. See the Power-On Reset section.
13
SCLK
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.
14
DGND
Digital Ground. Connect to pin 5.
15
DVDD
Digital Supply 5V
±5%. Bypass DVDD to DGND (pin 14) with a 0.1F capacitor.
16
DIN
Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.
17
CS
Chip Select Input. Drive
CS low to enable the serial interface. When CS is high, DOUT is high-impedance.
In external clock mode SSTRB is high-impedance when
CS is high.
18
CREF
Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1F.
19
AGND
Analog Ground. Connect pin 19 to pin 3.
20
AIN
Analog Input
Pin Description
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