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參數(shù)資料
| 型號： | MAX1149BCUP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 116KSPS 20-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 116k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
16
______________________________________________________________________________________
Digital Output
In unipolar input mode, the digital output is straight
binary (Figure 14). For bipolar input mode, the digital
output is two’s complement binary (Figure 15). Data is
clocked out on the falling edge of SCLK in MSB-first
format.
Clock Modes
The MAX1146–MAX1149 can use either the external
serial clock or the internal clock to drive the succes-
sive-approximation conversion. The external clock
shifts data in and out of the MAX1146–MAX1149.
External clock mode allows the fastest throughput rate
(116ksps) and serial clock frequencies from 0.1MHz to
2.1MHz. Internal clock mode provides the best noise
performance because the digital interface can be idle
during conversion. The internal clock mode serial clock
frequency can range from 0 to 2.1MHz. Internal clock
mode allows the CPU to request a conversion and
clock back the results.
Bits PD1 and PD0 of the control byte program the clock
and power-down modes. The MAX1146–MAX1149 power
up in internal clock mode with all circuits activated.
Figures 8–11 illustrate the available clocking modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, but it also drives the analog-to-
digital conversion. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and the results
appear at DOUT on each of the next 14 SCLK falling
edges (Figures 8 and10). SSTRB and DOUT go into a
high-impedance state when CS is high.
Use internal clock mode if the serial clock frequency is
less than 100kHz or if serial clock interruptions could
cause the conversion interval to exceed 140s. The
conversion must complete in 140s, or droop on the
T/H capacitors can degrade conversion results.
Internal Clock
When configured for internal clock mode, the
MAX1146–MAX1149 generate an internal conversion
clock. This frees the P from the burden of running the
SAR conversion clock and allows the conversion results
to be read back at the processor’s convenience, at any
clock rate up to 2.1MHz. SSTRB goes low at the start of
the conversion and then goes high when the conver-
sion is complete. SSTRB is low for a maximum of 8.0s,
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is in
progress. SCLK clocks the data out of this register at any
time after the conversion is complete. After SSTRB goes
high, the second falling SCLK clock edge produces the
MSB of the conversion at DOUT, followed by the remain-
ing bits in MSB-first format (Figures 9 and 11).
For the most accurate conversion, the MAX1146–
MAX1149 digital I/O should remain inactive during the
internal clock conversion interval (tCONV). Do not pull
CS high during conversion. Pulling CS high aborts the
current conversion. To ensure that the next start bit is
recognized, clock in 18 zeros at DIN. When internal
clock mode is selected, SSTRB does not go into a high-
impedance state when CS goes high. A rising edge on
SSTRB indicates that the MAX1146–MAX1149 have fin-
ished the conversion. The P can then read the conver-
sion results at its convenience.
SCLK
SSTRB
DIN
START SEL2
SEL1
SEL0
PD1
PD0
HIGH-Z
18
9
16
24
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS CONTROL BYTE
SET TO CB1
TRACK
HOLD
HIGH-Z
DOUT
tACQ
HIGH-Z
tCONV
CB1
OPEN
RESET TO CB1
D13
D12
D11
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
D7
CS
SGL/DIF UNI/BIP
Figure 8. External Clock Mode—24 Clocks/Conversion Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1149BCUP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 8Ch 116ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1149BCUP+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 8Ch 116ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1149BCUP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1149BEUP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1149BEUP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 8Ch 116ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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