參數(shù)資料
型號: MAX114EAG+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/12頁
文件大小: 0K
描述: IC ADC 8BIT 1MSPS 24-SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數(shù): 8
采樣率(每秒): 1M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 40mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 24-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極
Transfer Function
Figure 10 shows the MAX114/MAX118’s nominal trans-
fer function. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary
with 1LSB = (VREF+ - VREF-) / 256.
Conversion Rate
The maximum sampling rate (fMAX) for the MAX114/
MAX118 is achieved in write-read mode (tRD < tINTL),
and is calculated as follows:
where tWR = the write pulse width, tRD = the delay
between write and read pulses, tRI = RD to INT delay,
and tACQ = minimum acquisition time.
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limit-
ed to frequencies above DC and below one-half the
ADC sample rate.
The theoretical minimum analog-to-digital noise is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a per-
fect 8-bit ADC can do no better than 50dB.
The FFT Plot (see
Typical Operating Characteristics)
shows the result of sampling a pure 195.8kHz sinusoid
at a 1MHz rate. This FFT plot of the output shows the
output level in various spectral bands.
The effective resolution (or “effective number of bits”)
the ADC provides can be measured by transposing the
equation that converts resolution to SNR: N = (SINAD -
1.76) / 6.02 (see
Typical Operating Characteristics).
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal (in the frequency
band above DC and below one-half the sample rate) to
the fundamental itself. This is expressed as:
where V1 is the fundamental RMS amplitude, and V2
through VN are the amplitudes of the 2nd through Nth
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the amplitude of the
next largest spectral component (in the frequency
band above DC and below one-half the sample rate).
Usually the next largest spectral component occurs at
some harmonic of the input frequency. However, if the
ADC is exceptionally linear, it may occur only at a ran-
dom peak in the ADC’s noise floor. See the Signal-to-
Noise Ratio graph in
Typical Operating Characteristics.
THD = 20log
V
...V
V
2
3
2
4
2
N
2
1
+++
f=
1
t
+ t
f
1
250ns
150ns
160ns
f
1.23MHz
MAX
WR
RD
RI
ACQ
MAX
=
++
+
=
MAX114/MAX118
+5V, 1Msps, 4 & 8-Channel,
8-Bit ADCs with 1A Power-Down
______________________________________________________________________________________
11
OUTPUT CODE
INPUT VOLTAGE (LSBs)
FS
FS - 1LSB
FULL-SCALE
TRANSITION
12
3
11111111
11111110
11111101
00000011
00000010
00000001
00000000
1LSB =
VREF+ - VREF-
256
VREF-
VREF+
Figure 10. Transfer Function
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