with Internal Temperature Sensor and VDD
參數(shù)資料
型號(hào): MAX1153BEUE+T
廠商: Maxim Integrated Products
文件頁數(shù): 26/30頁
文件大?。?/td> 0K
描述: IC ADC 10BIT SYS MON 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 94k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 6.6mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極;4 個(gè)差分,單極;4 個(gè)差分,雙極
MAX1153/MAX1154
Stand-Alone, 10-Channel, 10-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1153), VDD = +4.5V to +5.5V (MAX1154), TA = TMIN to TMAX, unless otherwise noted.) (Note 1) (Figures 1,
2, and 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High Time
tCH
45
ns
SCLK Pulse Width Low Time
tCL
45
ns
DIN to SCLK Setup Time
tDS
25
ns
DIN to SCLK Hold Time
tDH
0ns
CS Fall to SCLK Rise Setup
tCSS
25
ns
SCLK Rise to CS Rise Hold
tCSH
50
ns
SCLK Fall to DOUT Valid
tDOV
CL = 30pF
50
ns
CS Rise to DOUT Disable
tDOD
CL = 30pF
40
ns
CS Fall to DOUT Enable
tDOE
CL = 30pF
40
ns
CS Pulse Width High
tCSW
50
ns
Note 1:
The devices are 100% tested at TA = +25°C and +85°C. Specification over temperature range is guaranteed by design.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been calibrated.
Note 3:
Offset nulled.
Note 4:
In reference mode 00, the reference system powers up for each temperature measurement. In reference mode 01, the ref-
erence system powers up once per sequence of channels scanned. If a sample wait <80s is programmed, the reference
system is on all the time. In reference mode 10, the reference system is on all the time (see Table 7).
Note 5:
No external capacitor on REF.
Note 6:
The operational input voltage range for each individual input of a differentially configured pair (AIN0–AIN7) is from GND to
VDD. The operational input voltage difference is from -VREF/2 to +VREF/2.
Note 7:
See Figure 3 and the Sampling Error vs. Input Source Impedance graph in the
Typical Operating Characteristics section.
Note 8:
Grade A tested at +10°C and +55°C. -20°C to +85°C and -40°C to +85°C specifications guaranteed by design. Grade B
tested at +25°C. TMIN to TMAX specification guaranteed by design.
Note 9:
External temperature measurement mode using an MMBT3904 (Diodes Inc.) as a sensor. External temperature sensing
from -40°C to +85°C; MAX1153/MAX1154 held at +25°C.
Note 10: Performing eight single-ended external channels’ temperature measurements, an internal temperature measurement, and
an internal VDD measurement with no sample wait results in a conversion rate of 2ksps per channel.
Note 11: Performing eight single-ended voltage measurements, an internal temperature measurement, and an internal VDD mea-
surement with no sample wait results in a conversion rate of 7ksps per channel.
Note 12: Performing eight single-ended voltage measurements, an internal temperature measurement, and an internal VDD mea-
surement with maximum sample wait results in a conversion rate of 3ksps per channel.
Note 13: Defined as the shift in the code boundary as a result of supply voltage change. VDD = min to max; full-scale input, mea-
sured using external reference.
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