參數(shù)資料
型號: MAX11601EKA+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/23頁
文件大?。?/td> 0K
描述: IC ADC SERIAL 8BIT 4CH SOT23-8
產(chǎn)品培訓模塊: MAX116xx
Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
位數(shù): 8
采樣率(每秒): 188k
數(shù)據(jù)接口: I²C,串行
轉換器數(shù)目: 1
功率耗散(最大): 1.75mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應商設備封裝: SOT-23-8
包裝: 標準包裝
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個差分,單極;2 個差分,雙極
產(chǎn)品目錄頁面: 1398 (CN2011-ZH PDF)
其它名稱: MAX11601EKA+TDKR
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Hold Time
tHD.DAT
(Note 12)
0
150
ns
Data Setup Time
tSU.DAT
10
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
(Note 13)
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
(Note 13)
20
160
ns
Fall Time of SCL Signal
tFCL
(Note 13)
20
80
ns
Rise Time of SDA Signal
tRDA
(Note 13)
20
160
ns
Fall Time of SDA Signal
tFDA
(Note 13)
20
160
ns
Setup Time for STOP Condition
tSU, STO
160
ns
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
010
ns
Note 1: The MAX11600/MAX11602/MAX11604 are tested at VDD = 5V and the MAX11601/MAX11603/MAX11605 are tested at VDD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) is configured to be an inter-
nal reference (SEL[2:1] = 11), decouple AIN_/REF or REF to GND with a 0.01F capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF or REF has a typical on-resistance of 675
.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P.
Note 10: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11: Power-supply rejection ratio is measured as:
,
for the MAX11601/MAX11603/MAX11605, where N is the number of bits.
Power-supply rejection ratio is measured as:
,
for the MAX11600/MAX11602/MAX11604, where N is the number of bits.
Note 12: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: CB = total capacitance of one bus line in pF. tR, tFDA, and tF measured between 0.3VDD and 0.7VDD. The minimum value is
specified at TA = +25°C with CB = 400pF.
Note 14: fSCLH must meet the minimum clock low time plus the rise/fall times.
VV
V
VV
FS
N
REF
55
45
2
55
45
..
() ()
[]×
VV
V
VV
FS
N
REF
33
27
2
33
27
..
() ()
[]×
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