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參數(shù)資料
| 型號(hào)： | MAX11605EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 5/23頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SERIAL 8BIT 12CH 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 188k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.75mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；12 個(gè)單端，雙極；6 個(gè)差分，單極；6 個(gè)差分，雙極 |
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Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then reads from the slave.
After the master has received the results, it can issue
an acknowledge if it wants to continue reading or a not
acknowledge if it no longer wishes to read. If the
MAX11600–MAX11605 receive a not acknowledge,
they release SDA, allowing the master to generate a
STOP or repeated START. See the
Clock Mode and
Scan Mode sections for detailed information on how
data is obtained and converted.
Clock Mode
The clock mode determines the conversion clock, the
acquisition time, and the conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s CLK bit determines the clock mode (Table
1). At power-up, the MAX11600–MAX11605 default to
internal clock mode (CLK = zero).
Internal Clock
When configured for internal clock mode (CLK = zero),
the MAX11600–MAX11605 use their internal oscillator
as the conversion clock. In internal clock mode, the
MAX11600–MAX11605 begin tracking analog input on
the ninth falling clock edge of a valid slave address
byte. Two internal clock cycles later, the analog signal
is acquired and the conversion begins. While tracking
and converting the analog input signal, the
MAX11600–MAX11605 hold SCL low (clock stretching).
After the conversion completes, the results are stored in
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________
13
110
1
00
0
R/W
A
SLAVE ADDRESS
S
SCL
SDA
1
234
567
89
DEVICE
SLAVE ADDRESS
1100100
1101101
MAX11600/MAX11601
MAX11602/MAX11603
1100101
MAX11604/MAX11605
Figure 7. Slave Address Byte
000
1
0X
X
A
HS MODE MASTER CODE
SCL
SDA
S
Sr
F/S MODE
HS MODE
Figure 8. F/S Mode to HS Mode Transfer
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX11606 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs |
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| MAX11606EUA | 制造商:MAXIM 功能描述:Pb Free |
| MAX11606EUA/V+ | 制造商:Maxim Integrated Products 功能描述:2.7V TO 3.6V AND 4.5V TO 5.5V, LOW-POWER, 4-/8-/12-CHANNEL - Rail/Tube |
| MAX11606EUA/V+T | 制造商:Maxim Integrated Products 功能描述:2.7V TO 3.6V AND 4.5V TO 5.5V, LOW-POWER, 4-/8-/12-CHANNEL - Tape and Reel |
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