參數(shù)資料
型號: MAX1179BCUI+T
廠商: Maxim Integrated Products
文件頁數(shù): 14/15頁
文件大小: 0K
描述: IC ADC 16BIT 135KSPS 28-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 135k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.03W
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,雙極
MAX1179/MAX1187/MAX1189
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
(AIN) charges capacitor CHOLD. The acquisition ends
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on CHOLD rep-
resents a sample of the input. In hold mode, the capac-
itive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of a 16-bit resolution. Force CS low to put
valid data on the bus after conversion is complete.
Power-Down Modes
Select standby mode or shutdown mode with R/C during
the second falling edge of CS (see Selecting Standby or
Shutdown Mode section). The MAX1179/MAX1187/
MAX1189 automatically enter either standby mode (ref-
erence and buffer on) or shutdown (reference and buffer
off) after each conversion depending on the status of
R/C during the second falling edge of CS.
Internal Clock
The MAX1179/MAX1187/MAX1189 generate an internal
conversion clock to free the microprocessor from the bur-
den of running the SAR conversion clock. Total conver-
sion time after entering hold mode (second falling edge of
CS) to end-of-conversion (EOC) falling is 4.7s (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1179/MAX1187/MAX1189 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start (CS) is
ignored if R/C is high. The MAX1179/MAX1187/
MAX1189 need at least 12ms (CREFADJ = 0.1F, CREF
= 10F) for the internal reference to wake up and settle
before starting the conversion, if powering up from
shutdown. Reset the MAX1179/MAX1187/ MAX1189 by
toggling RESET with CS high. The next falling edge of
CS begins acquisition.
Selecting Standby or Shutdown Mode
The MAX1179/MAX1187/MAX1189 have a selectable
standby or low-power shutdown mode. In standby
mode, the ADC’s internal reference and reference
buffer do not power down between conversions, elimi-
nating the need to wait for the reference to power up
before performing the next conversion. Shutdown mode
powers down the reference and reference buffer after
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
8
_______________________________________________________________________________________
Figure 2. MAX1179/MAX1187/MAX1189 Timing Diagram
tCSL
tCSH
tACQ
tDH
R/C
CS
EOC
D0–D15
tDS
tDV
tEOC
tDO
tBR
tCONV
HIGH-Z
REF POWER-
DOWN CONTROL
HIGH-Z
DATA VALID
Figure 3. Typical Application Circuit for the MAX1179/MAX1187/
MAX1189
MAX1179
MAX1187
MAX1189
ANALOG
INPUT
AIN
AVDD
+5V ANALOG
+5V DIGITAL
DVDD
D0–D15
16-BIT
WIDE
P DATA
BUS
10
F
0.1
F
0.1
F
0.1
F
R/C
CS
AGND DGND
REFADJ
REF
EOC
RESET
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