參數(shù)資料
型號: MAX1179CCUI+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/15頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 135KSPS 28-TSSOP
標準包裝: 2,500
位數(shù): 16
采樣率(每秒): 135k
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 1.03W
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,雙極
Transfer Function
Figures 8, 9, and 10 show the MAX1179/MAX1187/
MAX1189’s output transfer functions. The MAX1179
and MAX1189 outputs are coded in offset binary, while
the MAX1187 is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy and prevent loading the
source. Switch the channels immediately after acquisi-
tion, rather than near the end of or after a conversion
when the input signal is multiplexed. This allows more
time for the input buffer amplifier to respond to a large
step-change in input signal. The input amplifier must
have a high enough slew rate to complete the required
output voltage change before the beginning of the
acquisition time. Figure 11 shows an example of this
circuit using the MAX427.
Figures 12a and 12b show how the MAX1179 and
MAX1189 analog input current varies depending on
whether the chip is operating or powered down. The
part is fully powered down between conversions if the
voltage at R/C is set high during the second falling
edge of CS. The input current abruptly steps to the
powered up value at the start of acquisition. This step
in the input current can disrupt the ADC input, depend-
ing on the driving circuit’s output impedance at high
frequencies. If the driving circuit cannot fully settle by
the end of acquisition time, the accuracy of the system
can be compromised. To avoid this situation, increase
the acquisition time, use a driving circuit that can settle
within tACQ, or leave the MAX1179/MAX1189 powered
up by setting the voltage at R/C low during the second
falling edge of CS.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Do not run analog and digital lines parallel to each
other, and do not lay out digital signal paths under-
neath the ADC package. Use separate analog and dig-
ital ground planes with only one point connecting the
two ground systems (analog and digital) as close to the
device as possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
MAX1179/MAX1187/MAX1189
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
______________________________________________________________________________________
11
Figure 9. MAX1187 Transfer Function
OUTPUT CODE
65536
INPUT VOLTAGE (LSB)
INPUT RANGE = 0 TO +10V
2
1
03
65535
65534
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
FULL-SCALE RANGE
(FSR) = +10V
1LSB =
FSR x VREF
65536 x 4.096
FULL-SCALE
TRANSITION
Figure 10. MAX1189 Transfer Function
OUTPUT CODE
-32768
+32768
INPUT VOLTAGE (LSB)
INPUT RANGE = -10V TO +10V
0
-32766
-32767 -32765
+32767
+32766
-1
+1
11 . . . 1111
11 . . . 1110
11 . . . 1101
10 . . . 0001
10 . . . 0000
01 . . . 1111
00 . . . 0011
00 . . . 0010
00 . . . 0001
00 . . . 0000
FULL-SCALE RANGE
(FSR) = +20V
1LSB =
FSR x VREF
65536 x 4.096
FULL-SCALE
TRANSITION
Figure 8. MAX1179 Transfer Function
OUTPUT CODE
-32768
+32768
INPUT VOLTAGE (LSB)
INPUT RANGE = -5V TO +5V
0
-32766
-32767 -32765
+32767
+32766
-1
+1
11 . . . 1111
11 . . . 1110
11 . . . 1101
10 . . . 0001
10 . . . 0000
01 . . . 1111
00 . . . 0011
00 . . . 0010
00 . . . 0001
00 . . . 0000
FULL-SCALE RANGE
(FSR) = +10V
1LSB =
FSR x VREF
65536 x 4.096
FULL-SCALE
TRANSITION
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