參數(shù)資料
型號: MAX117EAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC ADC 8BIT 400KSPS 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 8
采樣率(每秒): 400k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 762mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 7 個單端,單極;7 個單端,雙極
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1A Power-Down
_______________________________________________________________________________________
7
_______________Detailed Description
Converter Operation
The MAX113/MAX117 use a half-flash conversion tech-
nique (see
Functional Diagram) in which two 4-bit flash
ADC sections achieve an 8-bit result. Using 15 com-
parators, the flash ADC compares the unknown input
voltage to the reference ladder and provides the upper
four data bits. An internal digital-to-analog converter
(DAC) uses the four most significant bits (MSBs) to
generate both the analog result from the first flash con-
version and a residue voltage that is the difference
between the unknown input and the DAC voltage. The
residue is then compared again with the flash com-
parators to obtain the lower four data bits (LSBs).
An internal analog multiplexer enables the devices to
read four (MAX113) or eight (MAX117) different analog
voltages under microprocessor (P) control. One of the
MAX117’s analog channels, IN8, is internally hard-
wired and always reads VREF+ when selected.
Power-Down Mode
In burst-mode or low-sample-rate applications, the
MAX113/MAX117 can be shut down between conver-
sions, reducing supply current to microamp levels (see
Typical Operating Characteristics). A logic low on the
PWRDN pin shuts the devices down, reducing supply
current typically to 1A when powered from a single
+3V supply. A logic high on
PWRDN wakes up the
MAX113/MAX117, and the selected analog input enters
the track mode. The signal is fully acquired after 900ns
(this includes both the power-up delay and the
track/hold acquisition time), and a new conversion can
be started. If the power-down feature is not required,
connect
PWRDN to VDD. For minimum current con-
sumption, keep digital inputs at the supply rails in
power-down mode. Refer to the
Reference section for
information on reducing the reference current during
power-down.
___________________Digital Interface
The MAX113/MAX117 have two basic interface modes,
which are set by the MODE pin. When MODE is low,
the converters are in read mode; when MODE is high,
the converters are set up for write-read mode. The A0,
A1, and A2 inputs control channel selection, as shown
in Table 1. The address must be valid for a minimum
time, tACQ, before the next conversion starts.
DATA
OUTPUTS
DATA
OUTPUTS
CL
RL = 3k
CL
a) HIGH-Z TO VOH
b) HIGH-Z TO VOL
RL = 3k
VDD
Figure 1. Load Circuits for Data-Access Time Test
DATA
OUTPUTS
10pF
3k
10pF
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
3k
VDD
DATA
OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
Table 1. Truth Table for Input Channel
Selection
MAX113
00
IN1
IN2
01
IN4
IN3
11
10
IN6
IN5
——
IN8
(reads VREF+ if selected)
IN7
——
00
1
01
1
01
0
10
1
11
1
11
0
10
0
MAX117
00
0
SELECTED CHANNEL
A2
A1
A0
A1
A0
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