Controllers with I2C/SP" />
參數(shù)資料
型號: MAX11800ETC+
廠商: Maxim Integrated Products
文件頁數(shù): 59/59頁
文件大小: 0K
描述: IC CTRLR TOUCH-SCREEN 12-TQFN
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 75
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
評估套件: 可供
數(shù)據(jù)接口: 串行,SPI?
數(shù)據(jù)速率/采樣率 (SPS,BPS): 105k
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 12-TQFN-EP(4x4)
包裝: 管件
產(chǎn)品目錄頁面: 1424 (CN2011-ZH PDF)
MAX11800–MAX11803
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I2C/SPI Interface
_______________________________________________________________________________________
9
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SDA, DIN, SCL, CLK, A0,
CS, A1)
Input Logic-High Voltage
VIH
0.7 x
VDD
V
Input Logic-Low Voltage
VIL
0.3 x
VDD
V
Input Leakage Current
IIN
VIN = 0V or VDD
-1
+1
μA
Input Hysteresis
VHYS
0.5 x
VDD
V
Input Capacitance
6
pF
DIGITAL OUTPUTS (SDA, DOUT,
TIRQ)
DOUT, ISOURCE = 1mA
0.9 x
VDD
Output Logic-High
VOH
TIRQ, CMOS configuration,
ISOURCE = 1mA
0.9 x
VDD
V
Output Logic-Low—
TIRQ, DOUT
VOL
ISINK = 1mA
0.4
V
Output Logic-Low—SDA
VOL
ISINK = 3mA
0.4
V
TIRQ Pullup Resistor
125
k
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.7V to 3.6V, TA = -40°C to +85°C (MAX11800E–MAX11803E), TA = -40°C to +105°C (MAX11800G/MAX11801G), unless oth-
erwise noted. Typical values are at TA = +25°C and VDD = 3.3V, unless otherwise noted.)
I2C TIMING CHARACTERISTICS
(VDD = 1.7V to 3.6V, TA = -40°C to +85°C (MAX11801E and MAX11803E), TA = -40°C to +105°C (MAX11801G), unless otherwise
noted. Typical values are at TA = +25°C and VDD = 3.3V, unless otherwise noted. See Figure 1.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
fSCL
0
400
kHz
Bus Free Time
tBUF
Bus free time between STOP and START
condition
1.3
μs
Hold Time for START Condition
tHD;STA
After this period, the first clock pulse is
generated
0.6
μs
SCL Pulse-Width Low
tLOW
1.3
μs
SCL Pulse-Width High
tHIGH
0.6
μs
Setup Time for Repeated START
(Sr) Condition
tSU;STA
0.6
μs
Data Hold Time
tHD;DAT
0
900
ns
Data Setup Time
tSU;DAT
100
ns
SDA and SCL Rise/Fall Time
tR, tF
Receiving
20 +
CB/10
300
ns
SDA and SCL Fall Time
tTF
Transmitting
20 +
CB/10
250
ns
Setup Time for STOP Condition
tSU;STO
0.6
μs
VDD = 1.7V to 2.7V
10
100
Bus Capacitance Allowed
CB
VDD = 2.7V to 3.6V
10
400
pF
Pulse Width of Suppressed Spike
tSP
50
ns
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