參數(shù)資料
型號(hào)： MAX1204AEAP+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 6/23頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 8CH 20-SSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 66
位數(shù)： 10
采樣率（每秒）： 133k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 640mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
14
Maxim Integrated
Figure 9. Internal Clock Mode Timing
SSTRB
CS
SCLK
DIN
DOUT
14
8
12
18
20
24
START
SEL2 SEL1 SEL0
UNI/
DIP
SGL/
DIF
PD1
PD0
B9
MSB
B8
B7
B0
LSB
S1
S0
ACQUISITION
1.5
s
(SCLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
10
s MAX
ADC STATE
2
3
5
6
7
9
10
11
19
21
22
23
tCONV
Data Framing
CS’s falling edge does not start a conversion on the
MAX1204. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on SCLK’s falling edge after the
eighth bit of the control byte (the PD0 bit) is clocked into
DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle; (e.g., after VDD is applied).
or
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress appears at DOUT.
If a falling edge on CS forces a start bit before B3
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1204 can run is 15 clocks/conversion. Figure 11a
shows the serial-interface timing necessary to perform
a conversion every 15 SCLK cycles in external clock
mode. If CS is low and SCLK is continuous, guarantee
a start bit by first clocking in 16 zeros.
Most microcontrollers (Cs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
conversion is typically the fastest that a C can drive
the MAX1204. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
PD0 CLOCK IN
tSSTRB
tCSH
tCONV
tSCK
SSTRB
SCLK
tCSS
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
CS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1204AEAP+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1204AEAP+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1204AEAP-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1204AEPP 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1204AEPP+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 8Ch 133ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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