參數(shù)資料
型號(hào): MAX1239MEEE+
廠商: Maxim Integrated Products
文件頁數(shù): 18/22頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SERIAL 16-QSOP
標(biāo)準(zhǔn)包裝: 100
位數(shù): 12
采樣率(每秒): 94.4k
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 666.7mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
輸入數(shù)目和類型: 12 個(gè)單端,單極;12 個(gè)單端,雙極;6 個(gè)差分,單極;6 個(gè)差分,雙極
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)
Serial Clock Frequency
fSCLH
(Note 13)
1.7
MHz
Hold Time, Repeated START
Condition (Sr)
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
160
ns
Data Hold Time
tHD, DAT
(Note 10)
0
150
ns
Data Setup Time
tSU, DAT
10
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
20
80
ns
Rise Time of SCL Signal after
Acknowledge Bit
tRCL1
Measured from 0.3VDD - 0.7VDD
20
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD - 0.7VDD
20
80
ns
Rise Time of SDA Signal
tRDA
Measured from 0.3VDD - 0.7VDD
20
160
ns
Fall Time of SDA Signal
tFDA
Measured from 0.3VDD - 0.7VDD (Note 11)
20
160
ns
Setup Time for STOP (P) Condition
tSU, STO
160
ns
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
(Notes 10 and 13)
0
10
ns
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)
Note 1: For DC accuracy, the MAX1236/MAX1238 are tested at VDD = 5V and the MAX1237/MAX1239 are tested at VDD = 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.1F capacitor and a 2k
Ω series resistor (see the Typical Operating Circuit).
Note 8: ADC performance is limited by the converter’s noise floor, typically 300VP-P.
Note 9: Measured as for the MAX1237/MAX1239
VV
V
VV
FS
REF
N
(.
)
( .
)
(.
.
)
36
27
21
36
27
[] ×
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