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參數(shù)資料
| 型號： | MAX125CEAX+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 14BIT 2X4CH 36-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 14 b |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 電源電壓： | ±4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
_______________________________________________________________________________________
5
CONDITIONS
ns
30
tCW
CONVST
Pulse Width
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(Figure 4)
(AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.)
ns
0
tCWS
CS
to WR Setup Time
ns
0
tCWH
CS
to WR Hold Time
ns
30
tWR
WR
Low Pulse Width
ns
125
tCSD
CS
to CONVST Delay
ns
30
tAS
Address Setup Time
ns
0
tAH
Address Hold Time
25pF load
ns
30
tID
RD
to INT Delay
ns
40
tRD
Delay Time Between Reads
ns
0
tCRS
CS
to RD Setup Time
ns
0
tCRH
CS
to RD Hold Time
ns
30
tRD
RD
Low Pulse Width
25pF load (Note 13)
ns
30
tDA
Data-Access Time
25pF load (Note 14)
ns
5
45
tDH
Bus-Relinquish Time
Mode 1, 1 channel
s
3
Mode 2, 2 channel
6
Mode 3, 3 channel
9
Mode 4, 4 channel
12
tCONV
Exiting shutdown
s
5
Start-Up Time
Note 1:
AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = ±5V (MAX125) or ±2.5V (MAX126).
Note 2:
Relative accuracy is the analog value’s deviation at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3:
CLK synchronized with CONVST.
Note 4:
fIN = 10.06kHz, VIN = ±5V (MAX125) or ±2.5V (MAX126).
Note 5:
First five harmonics.
Note 6:
All inputs except CH1A driven with ±5V (MAX125) or ±2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized.
Note 7:
Guaranteed by design. Not production tested.
Note 8:
AVDD = +5V, AVSS = -5V, DVDD = +5V, VIN = 0V (all channels).
Note 9:
Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as
TC = [
REFOUT/REFOUT] / T.
Note 10:
See Figure 2.
Note 11:
Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. VREFIN = 2.5V (internal).
Note 12:
Tested with VIN = AGND on all channels, VREFIN = 2.5V (internal).
Note 13:
The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of
Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 14:
The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF
capacitor. Thus, the time given is the part’s true bus-relinquish time, independent of the external bus loading capacitance.
Conversion Time
Mode 1, 1 channel
ksps
250
Conversion Rate/Channel
Mode 2, 2 channel
142
Mode 3, 3 channel
100
Mode 4, 4 channel
76
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