參數(shù)資料
    型號: MAX1267BCEG
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: ADC
    英文描述: 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
    中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
    封裝: 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24
    文件頁數(shù): 12/19頁
    文件大?。?/td> 307K
    代理商: MAX1267BCEG
    M
    265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
    with +2.5V Reference and Parallel Interface
    12
    ______________________________________________________________________________________
    External Acquisition
    Use external acquisition mode for precise control of the
    sampling aperture and/or dependent control of acquisi-
    tion and conversion times. The user controls acquisition
    and start of conversion with two separate write pulses.
    The first pulse, written with ACQMOD = 1, starts an
    acquisition interval of indeterminate length. The second
    write pulse, written with ACQMOD = 0 (all other bits in
    control byte unchanged), terminates acquisition and
    starts conversion on
    WR
    rising edge (Figure 5).
    The address bits for the input multiplexer must have the
    same values on the first and second write pulse.
    Power-down mode bits (PD0, PD1) can assume new
    values on the second write pulse (see
    Power-Down
    Modes
    section). Changing other bits in the control byte
    corrupts the conversion.
    Reading a Conversion
    A standard interrupt signal,
    INT
    , is provided to allow the
    MAX1265/MAX1267 to flag the μP when the conversion
    has ended and a valid result is available.
    INT
    goes low
    when the conversion is complete and the output data is
    ready (Figures 4 and 5). It returns high on the first read
    cycle or if a new control byte is written.
    Selecting Clock Mode
    The MAX1265/MAX1267 operate with either an internal
    or an external clock. Control bits D6 and D7 select
    either internal or external clock mode. The part retains
    the last-requested clock mode if a power-down mode is
    selected in the current input word. For both internal and
    external clock mode, internal or external acquisition
    can be used. At power-up, the MAX1265/MAX1267
    enter the default external clock mode.
    Internal Clock Mode
    Select internal clock mode to release the μP from the
    burden of running the SAR conversion clock. Bit D7 of
    the control byte must be set to 1 and bit D6 must be set
    to zero. The internal clock frequency is then selected,
    resulting in a conversion time of 3.6μs. When using the
    internal clock mode, tie the CLK pin either high or low
    to prevent the pin from floating.
    t
    CS
    t
    CSWS
    t
    WR
    t
    ACQ
    t
    CONV
    t
    DH
    t
    DS
    t
    INT1
    t
    D0
    t
    TR
    t
    CSWH
    ACQMOD = 1
    CS
    WR
    D11
    D0
    INT
    RD
    DOUT
    ACQMOD = 0
    VALID DATA
    CBYTE
    CONTROL
    BYTE
    HIGH-Z
    HIGH-Z
    Figure 5. Conversion Timing Using External Acquisition Mode
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