1. 參數(shù)資料
    型號: MAX1292BEEG+
    廠商: Maxim Integrated Products
    文件頁數(shù): 7/20頁
    文件大?。?/td> 0K
    描述: IC ADC 12BIT 400KSPS 24-QSOP
    產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
    Obsolescence Mitigation Program
    標準包裝: 50
    位數(shù): 12
    采樣率(每秒): 400k
    數(shù)據(jù)接口: 并聯(lián)
    轉換器數(shù)目: 1
    功率耗散(最大): 762mW
    電壓電源: 單電源
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
    供應商設備封裝: 24-QSOP
    包裝: 管件
    輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個偽差分,單極;2 個偽差分,雙極
    產(chǎn)品目錄頁面: 1396 (CN2011-ZH PDF)
    ___________Applications Information
    Power-On Reset
    When power is first applied, internal power-on reset cir-
    cuitry activates the MAX1290/MAX1292 in external
    clock mode and sets INT high. After the power supplies
    stabilize, the internal reset time is 10s, and no conver-
    sions should be attempted during this phase. When
    using the internal reference, 500s are required for
    VREF to stabilize.
    Internal and External Reference
    The MAX1290/MAX1292 can be used with an internal
    or external reference voltage. An external reference
    can be connected directly to REF or REFADJ.
    An internal buffer is designed to provide +2.5V at REF
    for both devices. The internally trimmed +1.22V refer-
    ence is buffered with a +2.05V/V gain.
    Internal Reference
    The full-scale range with the internal reference is +2.5V
    with unipolar inputs and ±1.25V with bipolar inputs. The
    internal reference buffer allows for small adjustments
    (±100mV) in the reference voltage (Figure 7).
    Note: The reference buffer must be compensated with
    an external capacitor (4.7F min) connected between
    REF and GND to reduce reference noise and switching
    spikes from the ADC. To further minimize reference
    noise, connect a 0.01F capacitor between REFADJ
    and GND.
    External Reference
    With the MAX1290/MAX1292, an external reference can
    be placed at either the input (REFADJ) or the output
    (REF) of the internal reference-buffer amplifier.
    Using the REFADJ input makes buffering the external
    reference unnecessary. The REFADJ input impedance
    is typically 17k
    .
    When applying an external reference to REF, disable
    the internal reference buffer by connecting REFADJ to
    VDD. The DC input resistance at REF is 25k
    .
    Therefore, an external reference at REF must deliver up
    to 200A DC load current during a conversion and
    have an output impedance less than 10
    . If the refer-
    ence has higher output impedance or is noisy, bypass
    it close to the REF pin with a 4.7F capacitor.
    Power-Down Modes
    To save power, place the converter in a low-current
    shutdown state between conversions. Select standby
    mode or shutdown mode using bits D6 and D7 of the
    control byte (Tables 1 and 2). In both software power-
    down modes, the parallel interface remains active, but
    the ADC does not convert.
    Standby Mode
    While in standby mode, the supply current is 1mA (typ).
    The part powers up on the next rising edge on WR and
    is ready to perform conversions. This quick turn-on time
    allows the user to realize significantly reduced power
    consumption for conversion rates below 400ksps.
    Shutdown Mode
    Shutdown mode turns off all chip functions that draw
    quiescent current, reducing the typical supply current
    to 2A immediately after the current conversion is com-
    pleted. A rising edge on WR causes the MAX1290/
    MAX1292 to exit shutdown mode and return to normal
    operation. To achieve full 12-bit accuracy with a 4.7F
    reference bypass capacitor, 500s is required after
    power-up. Waiting 500s in standby mode, instead of in
    full-power mode, can reduce power consumption by a
    factor of 3 or more. When using an external reference,
    MAX1290/MAX1292
    400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
    with +2.5V Reference and Parallel Interface
    ______________________________________________________________________________________
    15
    Table 5. Data-Bus Output (8 + 4 Parallel
    Interface)
    VDD = +5V
    330k
    50k
    GND
    50k
    0.01
    F
    4.7
    F
    REFADJ
    REF
    MAX1290
    MAX1292
    Figure 7. Reference Voltage Adjustment with External
    Potentiometer
    PIN
    HBEN = 0
    HBEN = 1
    D0
    Bit 0 (LSB)
    Bit 8
    D1
    Bit 1
    Bit 9
    D2
    Bit 2
    Bit 10
    D3
    Bit 3
    Bit 11 (MSB)
    BIPOLAR
    (UNI/BIP = 0)
    UNIPOLAR
    (UNI/BIP = 1)
    D4
    Bit 4
    Bit 11
    0
    D5
    Bit 5
    Bit 11
    0
    D6
    Bit 6
    Bit 11
    0
    D7
    Bit 7
    Bit 11
    0
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