
M
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
16
______________________________________________________________________________________
acquisition or conversion can cause additional supply-
noise, which may make it difficult to achieve true 12-bit
performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap configurations are not recommended, since the
layout should ensure proper separation of analog and
digital traces. Do not run analog and digital lines paral-
lel to each other, and don’t lay out digital signal paths
underneath the ADC package. Use separate analog
and digital PC board ground sections with only one
“star point” (Figure 11) connecting the two ground sys-
tems (analog and digital). For lowest noise operation,
ensure the ground return to the star ground’s power
supply is low impedance and as short as possible.
Route digital signals far away from sensitive analog and
reference inputs.
High-frequency noise in the power supply, V
DD
, could
impair operation of the ADC’s fast comparator. Bypass
V
DD
to the star ground with a network of two parallel
capacitors, 0.1μF and 4.7μF, located as close to the
MAX1294/MAX1296’s power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5
) if the
power supply is extremely noisy.
Figure 10. Timing Diagram for Fastest Conversion
Figure 11. Power-Supply and Grounding Connections
+5V
+5V
GND
SUPPLIES
DGND
+5V
COM
GND
4.7
μ
F
0.1
μ
F
V
DD
DIGITAL
CIRCUITRY
MAX1294
MAX1296
R* = 5
*OPTIONAL
CLK
ACQUISITION
CONTROL WORD
CONVERSION
D11–D0
ACQUISITION
SAMPLING INSTANT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
WR
RD
D7–D0
STATE
CONTROL
WORD
D11–
D0