參數(shù)資料
型號: MAX13047EETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/15頁
文件大小: 0K
描述: IC TRANSLATOR 2CH BIDIR 8-TDFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
邏輯功能: 變換器,雙向
位數(shù): 2
輸入類型: CMOS
輸出類型: CMOS
數(shù)據速率: 16Mbps
通道數(shù): 2
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 15ns
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-TDFN-EP(2x2)
包裝: 帶卷 (TR)
MAX13046E/MAX13047E
typical application involves interfacing a low-voltage
microprocessor to an external memory, such as the
DS2502. The maximum data rate depends on the
1-Wire device. For the DS2502, the maximum data rate
is 16.3kbps. A 5kΩ pullup resistor is recommended
when interfacing with the DS2502.
Push-Pull vs. Open-Drain Driving
The MAX13046E/MAX13047E can be driven in a push-
pull or open-drain configurations. For open-drain con-
figuration, internal 10kΩ resistors pull up I/O VL and I/O
VCC to their respective power supplies. See the Timing
Characteristics table for maximum data rates when
using open-drain drivers.
PCB Layout
The MAX13046E/MAX13047E require good PCB layout
for proper operation and optimal rise/fall time perfor-
mance. Ensure proper high-frequency PCB layout even
when operating at low data rates.
Driving High-Capacitive Load
Capacitive loading on the I/O lines impacts the rise time
(and fall time) of the MAX13046E/MAX13047E when dri-
ving the signal lines. The actual rise time is a function of
the load capacitance, parasitic capacitance, the supply
voltage, and the drive impedance of the MAX13046E/
MAX13047E.
Operating the MAX13046E/MAX13047E at a low data rate
does NOT increase capacitive load driving capability.
Single- and Dual-Bidirectional
Low-Level Translator
12
______________________________________________________________________________________
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
Figure 2b. Human Body Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
Ω
RD
1500
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 2a. Human Body ESD Test Model
100%
90%
60ns
10%
tr = 0.7ns TO 1ns
I PEAK
I
30ns
t
Figure 3b. IEC 61000-4-2 ESD Generator Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50M
Ω TO 100MΩ
RD
330
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 3a. IEC 61000-4-2 ESD Test Model
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