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參數(shù)資料
| 型號： | MAX132 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 18-Bit ADC with Serial Interface(±18-BIT，單通道，具有串行接口的ADC) |
| 中文描述： | ±18位ADC，串行接口 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 168K |
| 代理商： | MAX132 |
____________Func tional Desc ription
The MAX132 integrates the input voltage for a fixed
period of time, then deintegrates a known reference
voltage and measures the time required to reach zero.
Good line rejection is achieved by setting the (input)
integration time equal to one 50Hz or 60Hz period. The
MAX132 has a 50Hz/60Hz mode selection bit that sets
the integration time to 655/545 clock periods, respec-
tively, so that 50Hz/60Hz rejection is obtained with a
32,768Hz crystal. The MAX132 is tested and guaran-
teed at a 16 conv/sec throughput rate. Figure 1 shows
the basic MAX132 application circuit, with component
values selected for 16 conv/sec .
For applications that don’t require 50Hz/60Hz rejection,
the MAX132 will operate up to 100 conv/sec at reduced
accuracy (typically 0.012% FSR nonlinearity, or ±13
bits). In these applications, the 50Hz mode is recom-
mended because of its longer (655 count) integration
time. See Increased Speed section.
__________Analog Design Proc edure
Input V oltage Range
and Input Protec tion
The recommended analog full-scale input range is
±512mV. Performance is tested and guaranteed at
±512mV full scale, corresponding to a 2μV/LSB resolu-
tion at 18 bits. Resolution is defined as follows:
which corresponds to 2μV/LSB resolution at 18 bits.
Consult the Typical Operating Characteristics for Noise
vs. Number of Samples Averaged and other important
operating parameters. Note how accuracy depends on
common-mode input voltage (common mode is defined
here as
|
V
IN
LO - AGND
|
). For optimum performance,
set the analog input full-scale between ±470mV and
M
±18-Bit ADC with S erial Interfac e
6
_______________________________________________________________________________________
Re
/
(
) /
,
solution Volts LSB
V
FS
IN
]
=
262144
3k
3k
DOUT
DOUT
a Hgh-Z toV
OH
(t
8
)
b Hgh-Z toV
OL
(t
8
)
DGND
DGND
+5V
C
L
C
L
Figure 3. Load Circuits for Access Time
3k
3k
DOUT
DOUT
a V
OH
toHgh-Z (t
10
)
b V
OL
toHgh-Z (t
10
)
DGND
DGND
+5V
10pF
10pF
Figure 4. Load Circuits for Disable Time to Three-State
DIN
t
2
t
4
t
1
t
3
t
9
t
10
t
6
t
8
t
7
t
11
, t
12
t
5
SCLK
CS
DOUT
P0–P3
MSB IN
B6–B1
LSB IN
LSB OUT
B6–B1
MSB OUT
Figure 2. Serial-Mode Timing
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